1 S34063 1.5 a, step-up/down/ inverting switching regulators the stc 34063 series is a monolithic control circuit containing the primary functions required for dc?to?dc converters. these devices consist of an internal temperature compensated reference, comparator, controlled duty cycle oscillator with an active current limit circuit, driver and high current output switch. this series was specifically designed to be incorporated in step?down and step?up and voltage?inverting applications with a minimum number of external components. ? operation from 2.5 v to 30 v input ? low standby current ? current limiting ? output switch current to 1.5 a ? output voltage adjustable from 1.25 to 30v ? frequency operation from 100hz to 100 khz ? precision 1%reference figure 1. representative schematic diagram sq r q2 q1 100 i pk oscillator c t comparator + - 1.25 v reference regulator 1 2 3 4 5 6 7 8 drive collector i pk sense v cc comparator inverting input switch collector switch emitter timing capacitor gn d (bottom view) this device contains 51 active transistors. so?8 pdip?8 1 8 1 8 1 switch collector switch emitter timing capacitor gn d driver collector i pk sense v cc comparator inverting input (top view) 2 3 45 6 7 8 pin connections
S34063 2 maximum ratings rating symbol value unit power supply voltage v cc 40 vdc comparator input voltage range v ir -0.3 to + 40 vdc switch collector voltage v c(switch) 40 vdc switch emitter voltage (v pin 1 = 40 v) v e(switch) 40 vdc switch collector to emitter voltage v ce(switch) 40 vdc driver collector voltage v c(driver) 40 vdc driver collector current (note 1) i c(driver) 100 ma switch current i sw 1.5 a power dissipation and thermal characteristics plastic package, p, p1 suffix t a = 25 5 c p d 1.25 w thermal resistance r ja 100 5 c/w soic package, d suffix t a = 25 5 c p d 625 mw thermal resistance r ja 160 5 c/w operating junction temperature t j +150 5 c operating ambient temperature range t as s3406 0 to +70 storage temperature range t stg -65 to +150 5 c http://onsemi.com 3 electrical characteristics (v cc = 5.0 v, t a = t low to t high [note 4], unless otherwise specified.) characteristics symbol min typ max unit oscillator frequency (v pin 5 = 0 v, c t = 1.0 nf, t a = 25 5 c) f osc 24 33 42 khz charge current (v cc = 5.0 v to 40 v, t a = 25 5 c) i chg 24 35 42 a discharge current (v cc = 5.0 v to 40 v, t a = 25 5 c) i dischg 140 220 260 a discharge to charge current ratio (pin 7 to v cc , t a = 25 5 c) i dischg /i chg 5.2 6.5 7.5 - current limit sense voltage (i chg = i dischg , t a = 25 5 c) v ipk(sense) 250 300 350 mv output switch (note 5) saturation voltage, darlington connection (i sw = 1.0 a, pins 1, 8 connected) v ce(sat) - 1.0 1.3 v saturation voltage (note 6) (i sw = 1.0 a, r pin 8 = 82 to v cc , forced 20) v ce(sat) - 0.45 0.7 v dc current gain (i sw = 1.0 a, v ce = 5.0 v, t a = 25 5 c) h fe 50 75 - - collector off-state current (v ce = 40 v) i c(off) - 0.01 100 a comparator threshold voltage t a = 25 5 c t a = t low to t high v th 1.225 1.21 1.25 - 1.275 1.29 v threshold voltage line regulation (v cc = 5.0 v to 40 v) S34063 s33063 reg line - - 1.4 1.4 5.0 6.0 mv input bias current (v in = 0 v) i ib - -20 -400 na total device supply current (v cc = 5.0 v to 40 v, c t = 1.0 nf, pin 7 = v cc , v pin 5 > v th , pin 2 = gnd, remaining pins open) i cc - - 4.0 ma
S34063 3 t on v cc = 5.0 v pin 7 = v cc pin 5 = gnd t a = 25 5 c t off figure 2. output switch on-off time versus oscillator timing capacitor figure 3. timing capacitor waveform 0.01 0.02 0.05 0.1 0.2 0.5 1.0 2.0 5.0 10 c t , oscillator timing capacitor (nf) , output switch on-off time ( s) on-off m t 10 s/div , oscillator voltage (v) osc 200 mv/div v v cc = 5.0 v pin 7 = v cc pin 2 = gnd pins 1, 5, 8 = open c t = 1.0 nf t a = 25 5 c 1000 500 200 100 50 20 10 5.0 2.0 1.0 figure 4. emitter follower configuration output saturation voltage versus emitter current figure 5. common emitter configuration output switch saturation voltage versus collector current figure 6. current limit sense voltage versus temperature figure 7. standby supply current versus supply voltage 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 , saturation voltage (v) ce(sat) i e , emitter current (a) v v cc = 5.0 v pins 1, 7, 8 = v cc pins 3, 5 = gnd t a = 25 5 c (see note 7) , saturation voltage (v) ce(sat) 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 i c , collector current(a) v darlington connection forced = 20 -55 -25 0 25 50 75 100 125 , current limit sense voltage (v) ipk(sense) t a , ambient temperature ( 5 c) v v cc = 5.0 v i chg = i dischg 0 5.0 10 15 20 25 30 35 40 , supply current (ma) cc v cc , supply voltage (v) i c t = 1.0 nf pin 7 = v cc pin 2 = gnd 1.8 1.7 1.6 1.5 1.4 1.3 1.2 1.1 1.0 1.1 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 400 380 360 340 320 300 280 260 240 220 200 3.6 3.2 2.4 2.0 1.6 1.2 0.8 0.4 0 1.0 2.8 v cc = 5.0 v pin 7 = v cc pins 2, 3, 5 = gnd t a = 25 5 c (see note 7) 7. low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient temperature as poss ible.
S34063 4 170 h l 8 180 7 r sc 0.22 6 v in 12 v 100 + 5 r1 2.2 k r2 47 k sq r q2 q1 i pk osc c t v cc + - comp. 1.25 v ref reg 1 2 3 4 1n5819 c t 1500 pf 330 c o + v out 28 v/175 ma v out 1.0 h + 100 optional filter test conditions results line regulation v in = 8.0 v to 16 v, i o = 175 ma 30 mv = 0.05% load regulation v in = 12 v, i o = 75 ma to 175 ma 10 mv = 0.017% output ripple v in = 12 v, i o = 175 ma 400 mvpp efficiency v in = 12 v, i o = 175 ma 87.7% output ripple with optional filter v in = 12 v, i o = 175 ma 40 mvpp figure 8. step?up converter 9a. external npn switch 9b. external npn saturated switch (see note 8) 8 7 6 r sc v in 1 2 v out r r ? 0 for constant v in 8 7 6 r sc v in 1 2 v out figure 9. external current boost connections for i c peak greater than 1.5 a 8. if the output switch is driven into hard saturation (non?darlington configuration) at low switch currents ( 300 ma) and high driver currents ( 30 ma), it may take up to 2.0 s to come out of saturation. this condition will shorten the off time at frequencies 30 khz, and is magnified at high temperatures. this condition does not occur with a darlington configuration, since the output switch cannot saturate. if a non?darlington configuration is used, the following output drive condition is recommended.
S34063 5 1.25 v ref reg v out 5.0 v/500 ma 1.0 h v out + 100 optional filter 8 7 r sc 0.33 6 v in 25 v 100 + r1 1.2 k r2 3.6 k sq r q2 q1 i pk osc c t v cc + - comp. 1 2 3 4 c t 470 pf 470 c o + 5 l 1n5819 220 h test conditions results line regulation v in = 15 v to 25 v, i o = 500 ma 12 mv = 0.12% load regulation v in = 25 v, i o = 50 ma to 500 ma 3.0 mv = 0.03% output ripple v in = 25 v, i o = 500 ma 120 mvpp short circuit current v in = 25 v, r l = 0.1 a 1.1 a efficiency v in = 25 v, i o = 500 ma 83.7% output ripple with optional filter v in = 25 v, i o = 500 ma 40 mvpp figure 10. step?down converter 11a. external npn switch 11b. external pnp saturated switch 8 7 6 r sc v in 1 2 v out 8 7 6 r sc v in 1 2 v figure 11. external current boost connections for i c peak greater than 1.5 a
S34063 6 1.25 v ref reg v out -12 v/100 ma v out 1.0 h + 100 optional filter 8 7 r sc 0.24 6 v in 4.5 v to 6.0 v 100 + 5 r2 8.2 k sq r q2 q1 i pk osc c t comp. r1 953 1 2 3 4 + 1500 pf + - 1n5819 1000 f + 88 h v cc c o l test conditions results line regulation v in = 4.5 v to 6.0 v, i o = 100 ma 3.0 mv = 0.012% load regulation v in = 5.0 v, i o = 10 ma to 100 ma 0.022 v = 0.09% output ripple v in = 5.0 v, i o = 100 ma 500 mvpp short circuit current v in = 5.0 v, r l = 0.1 a 910 ma efficiency v in = 5.0 v, i o = 100 ma 62.2% output ripple with optional filter v in = 5.0 v, i o = 100 ma 70 mvpp figure 12. voltage inverting converter 13a. external npn switch 13b. external pnp saturated switch 8 7 6 v in 1 2 v out 8 7 6 v in 1 2 v out figure 13. external current boost connections for i c peak greater than 1.5 a
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